In some technologies, such as heterojunction bipolar transistor (HBT) devices, alloys such as SiGe may be used. In a SiGe HBT device, the base is formed in a SiGe layer and resides between an emitter and a collector. SiGe layers are provided by growing a layer in which Ge impurities are added to the Si lattice. In drift coupled SiGe HBT devices, the Ge profile may vary across the SiGe layer. The graded profile of the Ge provides energy band offsets that induce a drift field on charge carriers. Such conventional SiGe HBT devices may provide advantages over a silicon bipolar junction transistor in gain, frequency response, and noise parameters.
Another semiconductor technology includes MOS devices. FIG. 1 depicts a conventional MOS device 10. The MOS device 10 includes a includes a P-well 14 and an N-well 14′ formed in the substrate 12, as well as NMOS device 16 formed in the P-well 14 and a PMOS device 16′ formed in the N-well 14′. The NMOS device 16 includes a source 18, a drain 20, a channel 22, gate oxide 24, and a gate electrode 26. The source 18 and drain 20 have the same conductivity type, n+. The channel 20 is a p-type channel. The PMOS device 16′ includes a source 18′, a drain 20′, a channel 22′, gate oxide 24′, and a gate electrode 26′. The source 18′ and drain 20′ have the same conductivity type, p+. The channel 20′ is an n-type channel.
Current applications for semiconductor devices, such as the conventional MOS device 10, may require the conventional MOS device 10 to consume less power and have a higher speed. In order to meet such criteria, the conventional MOS device 10 is made smaller. Such a small conventional MOS device 10 pushes lithographic scaling limits. Consequently, strained silicon, high electron mobility transistor (HEMT), HHMT, and other exotic MOS technologies are increasingly being employed in fabricating the conventional MOS device 10.
Although small MOS devices 10 may be used, one of ordinary skill in the art will recognize that there are drawbacks. For example, the conventional MOS device 10 may suffer from a significant leakage current. In the linear region, the current for a conventional NMOS device 16 is given by:IDS=(½L)μnCoxW[2(VGS−VT)VDS−VDS2];  (1)
where VDS=applied bias voltage                L=length of channel        
As can be seen in Eqn. (1), even for a zero applied voltage (VDS=0), there is a theoretically a zero current, or a zero offstage leakage current. As the lengths of the channels 22/22′ are reduced, the offstage leakage current increases to the point where the MOS device 10 is never in a truly off state. This offstage leakage current penalty becomes very severe for MOS devices 10 in the sub-ninety nanometer range. This leakage current may pose significant problems to device designers because material selections other than silicon based are not yet optimized for high volume manufacturing.
Accordingly, what is needed is a method and system for reducing the offstage leakage current of the conventional MOS device 10. In addition, other mechanisms for tailoring the properties of the device continue to be desired. The present invention addresses such a need.